1. Field of the Invention
The present invention relates to a test method of an integrated circuit with a random-number generation circuit for testing a random-number generation circuit incorporated in an integrated circuit, and an integrated circuit with a random-number generation circuit.
2. Description of the Related Art
As described on pages 47 to 51 of Toshiba Review Vol. 58, No. 8 (2003), there have been increasing demands for high quality random numbers from an aspect of information security. It is desired to generate a random number that is difficult to predict in the case of communication and recording for encryption and decryption, device authentication, personal authentication, or access control to network. Under such circumstances, in a system LSI (large-scale integration), the random number has been generated by software. However, there have been an increasing number of cases that a random-number generation circuit by hardware is incorporated for a higher randomness. Because random number generation according to the software is based on an arithmetic algorithm, occurrence of periodicity is inevitable, and also occurrence of repeatability is inevitable such that, if the same initial value is provided, the same sequence of random number values is generated. On the other hand, in the random number generation according to the hardware using a physical phenomenon in principle, no periodicity is shown, setting of the initial value is not required, and the sequence of random number values generated after power-on reset will be different after each power-on reset.
In JP-A H11-312078 (KOKAI) and JP-A 2002-268874 (KOKAI), a random-number generation circuit configured by hardware is described. For example, in JP-A H11-312078 (KOKAI), resetting is not performed with respect to a random-number generation circuit configured by a linear feedback shift register (LFSR), so that random number values output from the random-number generation circuit immediately after power on are not the same, without setting the initial value. Further, in JP-A 2002-268874 (KOKAI), there is described a random-number-seed generation circuit that latches an output of a counter operating with a high-speed clock, which is output from an oscillator operating immediately after power on, by a latch circuit that uses a power-on reset signal as a trigger, and uses an output of the latch circuit as a random number seed value (initial value) for the random-number generation circuit. In this case, the count value (random number seed value) latched by the latch circuit is made different every time power is turned on, by using a fact that the power-on reset signal is sufficiently slower than the high-speed clock and an input timing thereof to the latch circuit varies for each time.
Such a random-number generation circuit by the hardware is incorporated in the system LSI after well reviewed in a designing stage. However, because an analog circuit element cannot be completely excluded in incorporation thereof, the random number characteristic may be affected depending on the quality of the random-number generation circuit itself. Therefore, at the time of designing and manufacturing the system LSI on trial, the operation thereof is confirmed by a circuit simulator such as a simulation program with integrated circuit emphasis (SPICE), operation confirmation and evaluation of the quality of the random number are performed by a programmable logic device (PLD) or a field programmable gate array (FPGA), and the quality of the random number needs to be evaluated again in a stage after the system LSI is manufactured. Further, it is desired that the evaluation result of the quality of the random number after the system LSI is manufactured is fed back to thereby enable adjustments of the random-number generation circuit.
Basically, evaluation of the quality of the random number is performed by a statistical test from various angles by obtaining a large amount of data. For example, according to tools published in NIST Special Publication 800-22 (hereinafter, NIST SP800-22) by National Institute of Standards and Technology (NIST), there are more than ten items such as a mono bit test and a poker test. In some of these tests, random number data of 100 million bits or more is required.
To ensure generation of good quality random numbers, all the items in the NIST SP800-22 need to be tested. However, when these tests are performed after the system LSI is manufactured, an actual machine evaluation test using an LSI evaluation board must be performed. If the actual machine evaluation test using the LSI evaluation board is newly added to a mass production process, the cost for the test becomes considerably large, and therefore it is not practical. Thus, under the current circumstances, there has been a strong demand for a method capable of efficiently testing the random-number generation circuit incorporated in the system LSI at a low cost in the mass production stage. To respond to such a demand, it is desired that the random-number generation circuit can be tested concurrently with the existing process without any interruption to it, during the existing process in the mass production stage.
Further, as described above, in random number generation by the software, the initial value needs to be provided after each power-on reset, and when the power is turned off, the random number value generated last needs to be stored as the initial value for the next power-on reset. On the other hand, in the case of the random-number generation circuit by the hardware, generally, such a process for the initial value is not required. This means that there is a strong need to check the quality of the random number sequence of the random-number generation circuit generated immediately after the power-on reset. It can be considered that if there is no problem in the quality of the random number sequence generated immediately after the power-on reset, the quality of the random number sequence subsequent thereto is guaranteed to some extent.